PMOS

Simple MOS Transistor

Library

Electrical/Analog/Semiconductors

Description

The PMOS model is a simple model of a p-channel metal-oxide semiconductor FET. It differs slightly from the device used in the SPICE simulator.

The model does not consider capacitances. A high drain-source resistance RDS is included to avoid numerical difficulties.

Some typical parameter sets are:

W       L      Beta        Vt       K2       K5       DW         DL

[m]     [m]    [A/V^2]     [V]      [-]      [-]      [m]        [m]

50.e-6  8.e-6  .0085e-3   -.15     .41      .839    -3.8e-6    -4.0e-6

20.e-6  6.e-6  .0105e-3  -1.0      .41      .839    -2.5e-6    -2.1e-6

30.e-6  5.e-6  .0059e-3   -.3      .98     1.01      0         -3.9e-6

30.e-6  5.e-6  .0152e-3   -.69     .104    1.1       -.8e-6     -.4e-6

30.e-6  5.e-6  .0163e-3   -.69     .104    1.1       -.8e-6     -.4e-6

30.e-6  5.e-6  .0182e-3   -.69     .086    1.06      -.1e-6     -.6e-6

20.e-6  6.e-6  .0074e-3  -1.       .4       .59      0          0

References: Spiro,H.: Simulation integrierter Schaltungen. R. Oldenbourg Verlag Muenchen Wien 1990.

Parameters

    PMOS_0

  • W [m] : Width (W): Scalar.
  • L [m] : Length (L): Scalar.
  • Beta [A/(V*V)] : Transconductance parameter (Beta): Scalar.
  • Vt [V] : Zero bias threshold voltage (Vt): Scalar.
  • K2 [-] : Bulk threshold parameter (K2): Scalar.
  • K5 [-] : Reduction of pinch-off region (K5): Scalar.
  • dW [m] : Narrowing of channel (dW): Scalar.
  • dL [m] : Shortening of channel (dL): Scalar.
  • RDS [Ohm] : Drain-Source-Resistance (RDS): Scalar.

Ports

  • Port 1 at left position: implicit input fixedport numbered 1.
  • Port 1 at right position: implicit output fixedport numbered 1.
  • Port 2 at right position: implicit output fixedport numbered 2.
  • Port 3 at right position: implicit output fixedport numbered 3.

See Also